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ORCIDVTS 1994: Cherry Hill, New Jersey, USA
- 12th IEEE VLSI Test Symposium (VTS'94), April 25-28, 1994, Cherry Hill, New Jersey, USA. IEEE Computer Society 1994, ISBN 0-8186-5440-6
- Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy:
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application. 2-7 - Irith Pomeranz, Sudhakar M. Reddy:
On identifying undetectable and redundant faults in synchronous sequential circuits. 8-14 - Aiman El-Maleh, Janusz Rajski:
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. 15-21 - Bernd Steinbach, M. Stöckert:
Design of fully testable circuits by functional decomposition and implicit test pattern generation. 22-27 - Sujit Dey, Srimat T. Chakradhar:
Retiming sequential circuits to enhance testability. 28-33 - Diego Vázquez, Adoración Rueda, José Luis Huertas:
A new strategy for testing analog filters. 36-41 - Mani Soma, Vladimir Kolarik:
A design-for-test technique for switched-capacitor filters. 42-47 - Abhijit Chatterjee, Rabindra K. Roy:
Design for diagnosability of linear digital filters using time-space expansion. 48-53 - Mustapha Slamani, Bozena Kaminska:
Multifrequency testability analysis for analog circuits. 54-59 - Michael F. Toner, Gordon W. Roberts:
A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADC. 60-65 - Dimitrios Kagaris, Spyros Tragoudas:
A design for testability technique for test pattern generation with LFSRs. 68-73 - Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer:
Test embedding with discrete logarithms. 74-80 - Danial J. Neebel, Charles R. Kime:
Multiple weighted cellular automata. 81-86 - Joan Carletta, Christos A. Papachristou:
Structural constraints for circular self-test paths. 87-92 - Kazuhiko Iwasaki, Akinori Furuta, Shigeo Nakamura:
Aliasing error for a mask ROM built-in self-test. 93-98 - Igor Rivin, Srimat T. Chakradhar:
Discrete test generation by continuous methods. 100-105 - Byung S. So, Charles R. Kime:
ICAT: incremental combinational ATPG. 106-113 - J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Test generation and three-state elements, buses, and bidirectionals. 114-121 - Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan:
Functional learning: a new approach to learning in digital circuits. 122-127 - Sreejit Chakravarty, Yiming Gong:
Diagnostic simulation of stuck-at faults in combinational circuits. 128-133 - Sayed Mohammad Kia, Sri Parameswaran
:
Novel architectures for TSC/CD and SFS/SCD synchronous controllers. 138-143 - Steffen Tarnick:
Controllable self-checking checkers for conditional concurrent checking. 144-150 - Michael Gössel, Egor S. Sogomonyan:
Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design. 151-157 - Michael Nicolaidis:
Efficient UBIST for RAMs. 158-166 - Piero Franco, Edward J. McCluskey:
On-line delay testing of digital circuits. 167-173 - John R. Wallack, Ramaswami Dandapani:
Coverage metrics for functional tests. 176-181 - Valery A. Vardanian:
On the complexity of terminal stuck-at fault detection tests for monotone Boolean functions. 182-185 - Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams:
Limitations in predicting defect level based on stuck-at fault coverage. 186-191 - Theo J. Powell, Kenneth M. Butler, Mike Ales, Roy Haley, Mark Perry:
Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]. 192-196 - Peter C. Maxwell:
Quality impacts of non-uniform fault coverage. 197-200 - Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
On compacting test sets by addition and removal of test vectors. 202-207 - Carolina L. C. Cooper, Michael L. Bushnell:
Neural models for transistor and mixed-level test generation. 208-213 - Paolo Camurati, Fulvio Corno, Michela Meo, Paolo Prinetto:
A new functional fault model for system-level descriptions. 214-219 - Soo Young Lee, Kewal K. Saluja:
Sequential test generation with reduced test clocks for partial scan designs. 220-225 - Loïc Vandeventer, Jean François Santucci, Norbert Giambiasi:
Speeding up behavioral test pattern generation using an algorithmic improvement. 226-231 - Shyam S. Somayajula, Edgar Sánchez-Sinencio, José Pineda de Gyvez:
A power supply ramping and current measurement based technique for analog fault diagnosis. 234-239 - José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva:
Architecture of test support ICs for mixed-signal testing. 240-246 - Janusz A. Starzyk, Zhi-Hong Liu, Jun Zou:
An organization of the test bus for analog and mixed-signal systems. 247-251 - Vladimir Kolarik, Marcelo Lubaszewski, Bernard Courtois:
Designing self-exercising analogue checkers. 252-257 - Ramesh Harjani, Bapiraju Vinnakota:
Analog circuit observer blocks. 258-263 - Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell:
FACTS: fault coverage estimation by test vector sampling. 266-271 - Xiaodong Xie, Alexander Albicki:
New advances in path delay fault testing of combinational circuits. 272-277 - Wuudiann Ke, Premachandran R. Menon:
Realization of fully path-delay-fault testable non-scan sequential circuits. 278-283 - Jacob Savir, Srinivas Patil:
On broad-side delay test. 284-290 - Weili Wang, Sandeep K. Gupta:
Weighted random robust path delay testing of synthesized multilevel circuits. 291-297 - Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Fault models and tests for Ring Address Type FIFOs. 300-305 - Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina:
An industrial experience in the built-in self test of embedded RAMs. 306-311 - Ad J. van de Goor, B. Smit:
Automating the verification of memory tests. 312-318 - Murali M. R. Gala, Peter Utama, Don E. Ross, Karan L. Watson:
Linear finite state machine for lD ILAs. 325-332 - Scott Glenn, Gavin Meil, Ed Rodriguez, Jeff Brooks:
Functional design verification for the PowerPC 601 microprocessor. 334-339 - G. Spiegel:
Fault probabilities in routing channels of VLSI standard cell designs. 340-347 - Sophie Crépaux-Motte, Mireille Jacomino, René David:
On robustness of required random test length with regard to fault occurrence hypotheses. 348-355 - Barbara Vasquez, Don R. Van Overloop, Scott E. Lindsey:
Known-good-die technologies on the horizon. 356-359 - Joel A. Jorgenson, Russell J. Wagner:
Analyzing the design-for-test techniques in a multiple substrate MCM. 360-365 - Eugeni Isern, Joan Figueras:
Analysis of IDDQ detectable bridges in combinational CMOS circuits. 368-373 - Adit D. Singh, Jason P. Hurst:
Incorporating IDDQ testing in BIST: improved coverage through test diversity. 374-379 - Christian Elm, Djamshid Tavangarian:
Fault detection and fault localization using IDDQ-testing in parallel testable FAST-SRAMs. 380-385 - Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs:
Circuit-level dictionaries of CMOS bridging faults. 386-391 - Michel Renovell, P. Huc, Yves Bertrand:
CMOS bridging fault modeling. 392-397 - Richard McGowen, F. Joel Ferguson:
Eliminating undetectable shorts between horizontal wires during channel routing. 402-407 - Hakim Bederr, Michael Nicolaidis, Alain Guyot:
Design for testability of on-line multipliers. 408-414 - Richard M. Sedmark:
Boundary-scan: beyond production test. 415-420 - M.-H. Gentil, Didier Crestani, Abdennour El Rhalibi, C. Durante:
A new high level testability measure: description and evaluation. 421-426 - Thomas Thomas, Praveen Vishakantaiah, Jacob A. Abraham:
Impact of behavioral modifications for testability. 427-432 - Siyad C. Ma, Edward J. McCluskey:
Open faults in BiCMOS gates. 434-439 - C.-J. Chen, Samiha Mourad:
Gate-to-channel shorts in BiCMOS logic gates. 440-445 - Brian Chess, Carl Roth, Tracy Larrabee:
On evaluating competing bridge fault models for CMOS ICs. 446-451 - Piero Franco, Edward J. McCluskey:
Three-pattern tests for delay faults. 452-456 - Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya:
Input pattern classification for transistor level testing of BiCMOS circuits. 457-462
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