default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID17. VDAT 2013: Jaipur, India
- Manoj Singh Gaur, Mark Zwolinski
, Vijay Laxmi, Dharmendar Boolchandani, Virendra Singh, Adit D. Singh:
VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers. Communications in Computer and Information Science 382, Springer 2013, ISBN 978-3-642-42023-8 - Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM. 1-9 - Gudlavalleti Rajahari, Yashu Anand Varshney, Subash Chandra Bose:
A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator. 10-18 - Vivek Verma, Chetan D. Parikh:
A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier. 19-25 - R. K. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar, Roy Paily:
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network. 26-34 - Shrirang Korde, Amol Khandare, Raghavendra B. Deshmukh, Rajendra M. Patrikar:
Computational Functions' VLSI Implementation for Compressed Sensing. 35-43 - Akhtar W. Alam, Esakkimuthu Dhakshinamoorthy, Prince Mathew, Narender Ponna:
A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization. 44-48 - Rahul Krishnamurthy, G. K. Sharma:
An Area Efficient Wide Range On-Chip Delay Measurement Architecture. 49-58 - Akhil Rathore, Chetan D. Parikh:
10 Gbps Current Mode Logic I/O Buffer. 59-65 - Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi:
Kapees: A New Tool for Standard Cell Placement. 66-73 - Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta:
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization. 74-82 - Sumanta Pyne, Ajit Pal:
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence. 83-93 - Amit Sharma, Ravindra Mukhiya, S. Santosh Kumar, B. D. Pant:
Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application. 94-99 - Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh:
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology. 100-107 - Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta:
Characterization of Logical Effort for Improved Delay. 108-117 - Ratul Kumar Baruah, Roy P. Paily:
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance. 118-127 - Somnath Paul, Abhijit Dana, Soumya Pandit:
An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design. 128-137 - Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Pravin Neminath Kondekar:
An Efficient RF Energy Harvester with Tuned Matching Circuit. 138-145 - Surabhi Singh, Brajesh Kumar Kaushik, Sudeb Dasgupta:
A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits. 146-152 - Jose Joseph, Rajendra M. Patrikar:
Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET. 153-159 - Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan:
Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). 160-168 - Mohd Anwar, Syed Azeemuddin, Mohammed Zafar Ali Khan:
Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs. 169-176 - Madhusoodan Agrawal, Alpana Agarwal:
A Combined CMOS Reference Circuit with Supply and Temperature Compensation. 177-184 - Sachin Maheshwari, Rameez Raza, Pramod Kumar, Anu Gupta:
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology. 185-193 - Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay, Prasenjit Basu, Bhaskar J. Karmakar:
A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures. 194-203 - Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor:
Random-LRU: A Replacement Policy for Chip Multiprocessors. 204-213 - Jainender Kumar, Manoj Kumar Majumder, Brajesh Kumar Kaushik, Sudeb Dasgupta:
Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations. 214-222 - Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy:
Congestion Balancing Global Router. 223-232 - Anirban Guha, Shubhajit Roy Chowdhury:
CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions. 233-241 - Saima Cherukat, Vineet Sahula:
Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption. 242-248 - Prashant Singh, Pooja Srivastava, Ram Mohan Verma, Saurabh Jaiswal:
Modeling of High Frequency Out-of-Plane Single Axis MEMS Capacitive Accelerometer. 249-256 - Sandip Ghosh, Rohit Srivastava:
CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time. 257-266 - Pankaj Kumar Pal, Brajesh Kumar Kaushik, Sudeb Dasgupta:
Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers. 267-273 - Sudip Roy, Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Krishnendu Chakrabarty:
On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics. 274-283 - Rohit Srivastava, Gaurav Gupta, Sarvesh Patankar, Nandini Mudgil:
Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and Tool. 284-293 - Vipul Singhal, Ayon Dey, Suresh Mallala, Somshubhra Paul:
A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup. 294-303 - Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, Mohit Baskota:
Fault Aware Dynamic Adaptive Routing Using LBDR. 304-311 - Nupur Navlakha, Lokesh Garg, Dharmendar Boolchandani, Vineet Sahula:
Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals. 312-321 - Joyati Mondal, Debesh Kumar Das, Dipak Kumar Kole, Hafizur Rahaman, Bhargab B. Bhattacharya:
On Designing Testable Reversible Circuits Using Gate Duplication. 322-329 - Kai Chi Alex Lam, Mark Zwolinski:
Circuit Transient Analysis Using State Space Equations. 330-336 - Anita Jain, Kavita Khare:
3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter. 337-344 - Jaynarayan T. Tudu, Deepak Malani, Virendra Singh:
Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. 345-352 - Cerin Ninan, Chandra Shekhar, M. Radhakrishna:
Design and Optimization of a 2x2 Directional Microstrip Patch Antenna. 353-360 - Pranab Roy, Samadrita Bhattacharya, Hafizur Rahaman, Parthasarathi Dasgupta:
A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips. 361-375 - Chidambaram Alagappan, Vishwani D. Agrawal:
Defect Diagnosis of Digital Circuits Using Surrogate Faults. 376-386
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-04-27 22:58 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
