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ORCIDAPCCAS 2023: Hyderabad, India
- IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023. IEEE 2023, ISBN 979-8-3503-8119-1
- Mayank Kumar Singh, Manish Kumar Gautam, Puneet Singh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare
:
A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs. 1-5 - Soumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, Nagendra Krishnapura:
A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur. 6-10 - Sumit Kumar, Nagendra Krishnapura:
Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis. 11-15 - Raviteja Kammari, Sarvesh Rajesh Tuckely, Vijay Shankar Pasupureddi:
A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS. 16-20 - Sandeep Soni, Gaurav Verma, Alok Kumar Shukla, Brajesh Kumar Kaushik:
Energy Efficient DSHE based Analogue Multiply Accumulate Computing Crossbar Architecture. 21-25 - Supriya Chakraborty, Tamoghno Das, Manan Suri:
Investigation of Voltage Fault Injection Attacks on NN Inference Utilizing NVM Based Weight Storage. 26-30 - Bharath Kumar Singh Muralidhar, Bakr Al Beattie, Max Uhlmann, Karlheinz Ochs, Gerhard Kahmen, Robert Rieger:
A Bio-Inspired CMOS Circuit for the Excitation and Inhibition of Neuronal Oscillators. 31-35 - Vemanaboina Vamsi, Kishor Sarawadekar:
FPGA Implementation of Inversion in Galois Field Over GF(2m) with FLT and ITA Using Quad Blocks. 36-39 - Ajay S, Praveen V. S, Kuruvilla Varghese:
An FPGA Based Accelerator of the Bi-Directional Wavefront Algorithm for Pairwise Sequence Alignment. 40-44 - Shivani Thakur, Srinivasu Bodapati:
Ternary Systolic Array Architecture for Matrix Multiplication in CNFET-Memristor Technology. 45-49 - Ralph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang:
A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process. 50-54 - Tanay Patni, Abhijit Pethe:
True Random Number Generator Implemented in ReRAM Crossbar Based on Static Stochasticity of ReRAMs. 55-59 - Sanmitra Bharat Naik, Asif Iqbal:
Digital to Pulse Converter for Analog in Memory Compute Applications. 60-64 - Noble G, Nalesh S, S. Kala:
Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA. 65-69 - Vikas Kumar, Santosh Parajuli, Shivansh Awasthi, Gayatri Ranade, Kartik Tyagi, Saheli Roy Chowdhury, Rahul Jaiswal, Thomas George Thundat, Ankur Gupta:
Passive RF Resonant Receiver with Voltage Gain for Wireless Power Transfer System. 70-74 - Dileep Kankipati, Madhu Munasala, Dasari Sai Nikitha, Satyapreet Singh Yadav, Sandeep Rao, Chetan Singh Thakur:
tinyRadar for Gesture Recognition: A Low-power System for Edge Computing. 75-79 - Richa Sharma, G. K. Sharma, Manisha Pattanaik:
Novel Label Flipping Dataset Poisoning Attack Against ML-Based HT Detection Systems. 80-84 - Jugal Gandhi, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey:
LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking. 85-89 - Jyoti Patel, Govind Sharma, Chitraja Rajan, Vivek Kumar, Sudeb Dasgupta:
Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET. 90-94 - Monika Pokharia, Ravi S. Hegde, Joycee Mekie:
Power-Efficient Approximate Multipliers Leveraging Hybrid CMOS-Memristor Paradigm. 95-99 - Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu:
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. 100-104 - Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu:
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. 105-109 - Soma Niloy Ghosh, Vineet Sahula, Lava Bhargava:
Reinforcement Learning Based Prefetch-Control Mechanism. 110-114 - Harshith Nimmagadda, Anshu Sarje:
Comparative Analysis of SPAD Models for Low-Light Imaging. 115-119 - Anjali Singh, Vikranth Varma Kosuri, Anshu Sarje:
Implementation and Comparative Analysis of Flexible Micro-Heater Circuits for Lab-on-a-chip Applications. 120-124 - Feng Yan, Kangkang Sun, Zhipeng Li, Jian Guan, Bingjun Xiong, Jingjing Liu:
A High-Impedance 3-MOSFET Pseudo-Resistor for Instrumentation Amplifiers of Biomedical Sensors. 125-128 - Adithya Sunil Edakkadan, Abhishek Srivastava:
Deep Learning Based Portable Respiratory Sound Classification System. 129-133 - Yuxuan Huang, Feng Yan, Kangkang Sun, Jingjing Liu:
A Self-Biased Subthreshold CMOS Voltage Reference with Temperature Compensation Circuit for IoT Self-Powered Sensor Applications. 134-138 - Anik Batabyal, Rajesh H. Zele:
A 197 dBc/Hz FoMT 24.8-28.97 GHz Class-F VCO Using Single-Turn Multi-Tap Inductor. 139-143 - Endersh Soni, Saravana Manivannan:
Analysis of Switched-RC N-path filters with Finite Switch Resistance and Switched $G_{m}-C$ filters using the Adjoint Network. 144-148 - Mohmad Aasif Bhat, Imon Mondal:
A Low-Loss, Compact Wideband True-Time-Delay Line for Sub-6GHz Applications Using N - Path Filters. 149-153 - Sayan Banerjee, Ankesh Jain:
Modified Gm-Free Assisted Opamp Technique in Continuous Time Delta Sigma Modulators. 154-158 - Sagar Mahajan, Poulami Mandal, Laxmeesha Somappa:
Low Precision Floating Point Spectral Feature Extraction Engine for Closed-Loop Neuromodulation. 159-163 - Sebastian Simmich, Patrick Wiegand, Robert Rieger:
Noise Efficient Three-Channel Amplifier for MEMS Cantilever Readout. 164-168 - Kamran Naderi Beni, Matthias Christoph Eger, Nils G. Margraf, Robert Rieger:
Sensor Node with Position Validation towards Camptocormia Measurement at Home. 169-172 - Hitesh Sahu, Emon Sarkar, Laxmeesha Somappa:
Implementation of FFT Using Low-Precision Floating Point for Rapid High Precision MEMS Readouts. 173-177 - Pushkar Sathe, Ajay Verma, Laxmeesha Somappa:
Efficient CORDIC Architectures for FFT Based All Digital Resonator Frequency Estimation. 178-182 - Kartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu:
A Novel Low-Power Shift-Register Controller for Digital Low-Dropout Regulators. 183-187 - Raghav Bansal, Shouri Chatterjee:
A 95-nA Quiescent-Current Fast-Transient Output-Capacitor-Less LDO with Enhanced Load Regulation for IoT Applications. 188-192 - Anup J. Deka, Biswarup Rana, Shuvoshree Bhattacharya:
A Novel Architecture with Nullified Parasitic Capacitance for Accurate FuSa Detection. 193-196 - Nishant Kumar, Hari Shanker Gupta, Nilesh M. Desai, Nihar Ranjan Mohapatra:
Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics. 197-201 - Wangchen Fan, Zhongyuan Fang, Yongjia Li, Minggang Chen, Weifeng Sun:
A Transient-Enhanced Capacitor-Less LDO With 30-MHz Bandwidth and High Slew Rate. 202-206 - Tapas Nandy, Ashish Joshi, Sanjoy Kumar Dey:
Large Network of Wide- Range Analog Voltage Observers for Debug & Testability. 207-211 - Surya Naga Aditya V. Dupukuntla, Koushik Sai Nimmaturi, Tamal Mandal, Sathwik Abramoni, Sudip Roy:
Efficient Dilution of a Fluid from its Related Arbitrary Stock Solutions using MEDA Biochips. 212-216 - K. Akhilesh Rao, Laxmeesha Somappa:
An 8-Channel TDM Spectral Feature Extraction for Neuromodulation SoC. 217-221 - Yicong Shao, Chao Wang, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li:
V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. 222-226 - Ketan Atul Bapat, Mrityunjoy Chakraborty:
Exploiting Node Level Algorithm Diversity for Distributed Compressed Sensing. 227-231 - Anubhav Mishra, Nanditha Rao, Ganesh Gore, Xifan Tang:
Architectural Exploration of Heterogeneous FPGAs for Performance Enhancement of ML Benchmarks. 232-235 - Basamgari Bhanu Prakash Reddy, Nitish Kumar, Kavindra Kandpal, Manish Goswami:
Multiplexer & Memory Efficient Bit-Reversal Algorithms. 236-240 - Zainab Aizaz, Kavita Khare, Mohd Anas Khan, Mahesh Kumar Singh, Vaithiyanathan Dhandapani:
A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs. 241-245 - Tika Ram Pokhrel, Alak Majumder:
Double Gate JLT Based New TIGFET for Dynamic C2MOS Application. 246-250 - Ashish Joshi, Tapas Nandy, Aashish T. R, Mayank Devam, Sanjoy Kumar Dey:
Modelling the Effect of Output-Dependent Integrator Gain on the Unadjusted Error of Inverter Based 1stOrder $\Sigma\Delta$ ADC. 251-255 - Kangkang Sun, Feng Yan, Huan Wu, Jingjing Liu:
A 0.6V 10-bit 20kHz Capacitor Splitting Bypass Window SAR ADC for Biomedical Applications. 256-260 - Bipul Boro, Ashvinikumar Dongre, Rushik Parmar, Gaurav Trivedi:
Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing. 261-265 - Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang:
2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. 266-270 - Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. 271-275 - Yusuke Toyoshima, Ryosuke Kamiya, Kenichi Ohhata:
High-Precision Open-Loop Time Amplifier Using Current Regulator. 276-279 - Mayank Anupam, Imon Mondal:
A Robust Overdesign Prevention Circuit Technique Under Widely Varying Ambient Conditions. 280-284 - Joel Thomas, Jai Narayan Tripathi:
Radial Basis Function Based Surrogate-Assisted Metaheuristic Approach for Variability Analysis. 285-288 - Sandeep Kodam, Wilfred Kisku, Amandeep Kaur, Deepak Mishra:
On Edge FPN Reduction in CMOS Image Sensor Using CNN with Attention Mechanism. 289-293 - Swatilekha Majumdar:
CAWPR: Contention Aware Write Preemptive Management Policy for Hybrid Last Level Caches. 294-298 - Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi:
Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs. 299-303 - Alfonso Rafael Cabrera-Galicia, Arun Ashok, Patrick Vliex, Andre Kruth, Andre Zambanini, Stefan van Waasen:
A Cryogenic Voltage Regulator with Integrated Voltage Reference in 22 nm FDSOI Technology. 304-308 - A. BhanuPrasad, Kuruvilla Varghese:
High Throughput Hardware Acceleration for Image Generation using HLS. 309-313 - Wilfred Kisku, Prateek Khandelwal, Amandeep Kaur, Deepak Mishra:
An Intelligent CMOS Image Sensor System Using Edge Information for Image Classification. 314-318 - Mohammed Mujahid Ulla Faiz, Azzedine Zerguine, Izzet Kale:
ECG Artifacts Suppression Using the NLSRA-Based Cascaded Fixed Point Interference Canceller. 319-322 - Xiao-Juan Huang, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang, Sau-Gee Chen:
A MATE-GDBF Algorithm for Irregular Punctured LDPC Codes and Its Decoder Implementation. 323-327 - Biswajit Mishra, Purvi Patel:
Energy Harvester Powered Fully Digital ECG Front End Acquisition with Integrated TDC. 328-332 - Palash Das, Hemangee K. Kapoor:
NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism. 333-337 - Purvi Patel, Biswajit Mishra:
All Digital Minimum Energy Point Detection for Ultra Low Power CMOS Circuits. 338-342 - Sadhu Sai Ram, Kuruvilla Varghese:
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder. 343-347 - Tantep Sinjanakhom, Sorawat Chivapreecha:
Real-Time Zero-Phase Digital Filter Using Recurrent Neural Network. 348-352 - Sourav Karmakar, Anshu Sarje, Aftab M. Hussain:
Design and Characterization of Quantum Cellular Automata (QCA) Based Optimized Circuits for Emerging Technologies. 353-357 - Arpit Sahni, Abhishek Srivastava:
Design of a Wideband 8-20 GHz Receiver Front-End with Reduced Local Oscillator Phase-Error in 4-Path Mixer. 358-362 - Mayur S. Marinaik, Naveen Kadayinti:
Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs. 363-366 - Hideaki Okazaki:
On a Piecewise Linear Function Approximation for Quantum Computation. 367-370 - S. Tarun Varma, Krishna Kanth Avalur:
A 0.9V Current-Mode Bandgap Reference with Wideband PSRR Better than 70dB from -40°C to 75°C. 371-374 - Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy:
An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range. 375-377
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last updated on 2026-04-29 00:09 CEST by the dblp team
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