"A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process."

Jhih-Ying Ke et al. (2023)

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DOI: 10.1109/APCCAS60141.2023.00068

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-10

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Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. APCCAS 2023: 271-275

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