"An FPGA-based bit-level weight sparsity and mixed-bit accelerator for ..."

Xianghong Hu et al. (2025)

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DOI: 10.1016/J.SYSARC.2025.103463

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type: Journal Article

metadata version: 2025-11-14

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Xianghong Hu, Shansen Fu, Yuanmiao Lin, Xueming Li, Chaoming Yang, Rongfeng Li, Hongmin Huang, Shuting Cai, Xiaoming Xiong:
An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks. J. Syst. Archit. 166: 103463 (2025)

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