"Low power driven re-synthesis algorithm for heterogeneous FPGA under delay ..."

Po-Xun Chiu et al. (2001)

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DOI: 10.1109/ISCAS.2001.922099

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh:
Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. ISCAS (5) 2001: 519-522

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