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ORCIDISCAS 2001: Sydney, Australia - Volume 5
- Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001. IEEE 2001, ISBN 0-7803-6685-9
- Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura:
IEEE1394 system simulation environment and a design of its link layer controller. 1-4 - Alexander Zemliak:
System design problem formulation by control theory. 5-8 - Lukai Cai, Daniel Gajski, Mike Olivarez:
Introduction of system level architecture exploration using the SpecC methodology. 9-12 - Jong-Yeol Lee, In-Cheol Park
:
Global variable localization and transformation for hardware synthesis from high-level programming language description. 13-16 - Lévis Thériault, Daniel Audet, Yvon Savaria:
Performance estimators for hardware/software co-design. 17-20 - Anthony Vetro, Huifang Sun:
Encoding and transcoding multiple video objects with variable temporal resolution. 21-24 - Guobin Shen, Bing Zeng, Ya-Qin Zhang, Ming L. Liou:
Transcoder with arbitrarily resizing capability. 25-28 - Kai-Tat Fung, Yui-Lam Chan, Wan-Chi Siu:
Low-complexity and high quality frame-skipping transcoder. 29-32 - Chia-Wen Lin, Jian Zhou, Ming-Ting Sun, Hung Hseng Hsu:
Minimum cost implementation of full VCR functionality in MPEG video streaming. 33-36 - Wilfried Zeise, Anton Kummert:
A new image interpolation method for increasing the frame rate in multimedia and virtual reality applications. 37-40 - Euiseok Kim, Dong-Ik Lee:
A new resource constrained asynchronous scheduling method through transformation of dataflow graphs. 41-44 - Hen-Ming Lin, Jing-Yang Jou:
On tri-state buffer inference in HDL synthesis. 45-48 - Po-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai:
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture. 49-52 - Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie:
An automatic word length determination method. 53-56 - Mustahsan Mir, Mohammed A. Al-Saleh:
A constructive procedure for optimizing the placement of macrocells. 57-60 - Bogdan J. Falkowski, Sudha Kannurao:
Calculation of sign Walsh spectra of Boolean functions from disjoint cubes. 61-64 - Junaid A. Khan, Sadiq M. Sait, Salman A. Khan:
A fast constructive algorithm for fixed channel assignment problem. 65-68 - Mauro Olivieri:
A genetic approach to the design space exploration of superscalar microprocessor architectures. 69-72 - Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie:
An efficient BIST method for testing of embedded SRAMs. 73-76 - Fong-Ming Shyu, Sao-Jie Chen:
A distributed and object-oriented framework for VLSI physical design automation. 77-80 - Kangmin Lee, Chi Weon Yoon, Ramchan Woo, Jeong-Hun Kook, Ja-Il Koo, Tae-Sung Jung, Hoi-Jun Yoo:
A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator. 81-84 - Kisun Kim, Taekyoon Ahn, Sang-Yeol Han, Chang-Seung Kim, Ki-Hyun Kim:
Low-power multiplexer decomposition by suppressing propagation of signal transitions. 85-88 - Kazutoshi Kobayashi, Hidetoshi Onodera:
ST: PERL package for simulation and test environment. 89-92 - Md. Abdur Razzak, Bing Zeng:
Multiple description image transmission for diversity systems using block-based DC separation. 93-96 - Feng Wu, Shipeng Li, Ya-Qin Zhang:
Progressive fine granular scalable (PFGS) video using advance-predicted bitplane coding (APBIC). 97-100 - Supavadee Aramvith, Chia-Wen Lin, Sumit Roy, Ming-Ting Sun:
Wireless video transport using conditional retransmission and low-delay interleaving. 101-104 - Nikolaos V. Boulgouris, Athanasios Leontaris, Nikolaos Thomos, Michael G. Strintzis:
Robust layered coding of video for transmission over noisy channels. 105-108 - Wenwu Zhu, Qian Zhang, Ya-Qin Zhang:
Network-adaptive rate control with unequal loss protection for scalable video over Internet. 109-112 - S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti:
Symbolic verification of Boolean constraints over partially specified functions. 113-116 - Wei Wang, Malgorzata Chrzanowska-Jeske:
A global approach to the variable ordering problem in PSBDDs. 117-120 - Sherief Reda, Ayman Wahba, Ashraf Salem, Dominique Borrione, M. Ghonaimy:
On the use of don't cares during symbolic reachability analysis. 121-124 - Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti:
Abstractions for model checking of event timings. 125-128 - Lubomir Ivanov, Ramakrishna Nunna:
Modeling and verification of cache coherence protocols. 129-132 - Sumohana S. Channappayya, Glen P. Abousleman, Lina J. Karam:
Joint source-channel coding of images using punctured convolutional codes and trellis-coded quantization. 133-136 - Qian Zhang, Wenwu Zhu, Zhu Ji, Ya-Qin Zhang:
A power-optimized joint source channel coding for scalable video streaming over wireless channel. 137-140 - Quji Guo, Qian Zhang, Wenwu Zhu, Ya-Qin Zhang:
A sender-adaptive and receiver-driven layered multicast scheme for video over Internet. 141-144 - John McEachen, Abdullah Cay:
Masking compressed video connection utilization in ATM networks. 145-148 - Mohammed E. Al-Mualla, Cedric Nishan Canagarajah, David R. Bull:
Multiple-reference temporal error concealment. 149-152 - Tsutomu Yamaoki, Satoshi Taoka, Toshimasa Watanabe:
Extracting a planar spanning subgraph of a terminal-vertex graph by solving the independent set problem. 153-156 - Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj:
A variable partition approach for disjoint decomposition. 157-162 - Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu:
Adaptive negative cycle detection in dynamic graphs. 163-166 - Shun-Wen Cheng, Kuo-Hsing Cheng:
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. 167-170 - Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Evolutionary graph generation system with transmigration capability for arithmetic circuit design. 171-174 - Hong Li, Bee June Tye, Ee Ping Ong, Weisi Lin, Chi Chung Ko:
Multiple motion object segmentation based on homogenous region merging. 175-178 - Kam-Fai Chan, Y. T. Wong, Chi-Wah Kok:
Multiresolution mesh representation using vertex cluster contraction. 179-182 - Alexis M. Tourapis, Oscar C. Au, Ming L. Liou:
New results on zonal based motion estimation algorithms-advanced predictive diamond zonal search. 183-186 - Wujian Zhang, Runde Zhou, Toshio Kondo:
Low-power motion-estimation architecture based on a novel early-jump-out technique. 187-190 - Christoph Scholl, Marc Herbstritt, Bernd Becker:
Exploiting don't cares to minimize *BMDs. 191-194 - Sudhakar Bobba, Ibrahim N. Hajj:
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. 195-198 - Janusz A. Starzyk, Dong Liu:
Multiple fault diagnosis of analog circuits by locating ambiguity groups of test equation. 199-202 - Hiroshi Tsutsui, K. Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura:
A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression. 203-206 - Mei-Juan Chen, Chih-Wei Pan, Jeng-Wei Chen, Ro-Min Weng:
Multiple region-of-interest image coding with embedded watermark. 207-210 - Simon Tredwell, Adrian N. Evans:
Block grouping algorithm for motion description encoding. 211-214 - Richard P. Kleihorst, Anteneh A. Abbo, André van der Avoird, M. Op de Beeck, Leo Sevat, Paul Wielage, R. van Veen, H. van Herten:
Xetal: a low-power high-performance smart camera processor. 215-218 - Jian Feng, Tie-Yan Liu, Kwok-Tung Lo, Xu-Dong Zhang:
Adaptive motion tracking for fast block motion estimation. 219-222 - Bedabrata Pain, Suresh Seshadri, Monico Ortiz, Chris Wrigley, Guang Yang:
CMOS imager with charge-leakage compensated frame difference and sum output. 223-226 - Chung-Neng Wang, Tihao Chiang, Chi-Min Liu, Hung-Ju Lee:
Improved MPEG-4 visual texture coding using double transform coding. 227-230 - Hua Cai, Bing Zeng:
A new SPIHT algorithm based on variable sorting thresholds. 231-234 - K. H. Leung, Bing Zeng:
Wavelet-based digital watermarking with halftoning technique. 235-238 - Jiwu Huang, Yun Q. Shi:
Embedding gray level images. 239-242 - Ming Sun Fu, Oscar C. Au:
Improved halftone image data hiding with intensity selection. 243-246 - Tobias Schüle, Albrecht P. Stroele:
Scheduling tests for low power built-in self-test. 247-250 - Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Power constrained test scheduling using power profile manipulation. 251-254 - Valentina Muresan, Xiaojun Wang, Mircea Vladutiu:
A combined tree growing technique for block-test scheduling under power constraints. 255-258 - Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An AVPG for SOC design verification with port order fault model. 259-262 - Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon:
Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. 263-266 - Sunho Chang, Lee-Sup Kim:
Design trade-off in merged DRAM logic for video signal processing. 267-270 - Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang:
Adaptive postprocessors with DCT-based block classifications. 271-274 - Shao-Yi Chien, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen:
A hybrid morphology processing units architecture for real-time video segmentation systems. 275-278 - M. Kacarska, Suzana Loskovska, D. Andonov:
The advantages of multiprocessor systems for ACEIT and ICEIT inverse problem solution. 279-282 - K. A. Jung, Y. S. Lee, H. S. Yang, W. S. Yang, JooHyoung Kim, Seung-Ho Lee, B. H. Kang:
An integrated H.263 video CODEC with protocol processor. 283-286 - Wen-Nung Lie, Bo-Er Wei:
Intermediate view synthesis from binocular images for stereoscopic applications. 287-290 - Andrew G. Dempster, Cecilia Di Ruberto:
Using granulometries in processing images of malarial blood. 291-294 - D. R. Clewer, L. J. Luo, Cedric Nishan Canagarajah, David R. Bull, M. H. Barton:
Efficient multiview image compression using quadtree disparity estimation. 295-298 - Lizhong Peng, Minghui Wang:
An embedded wavelet-based quadtree interframe coding algorithm. 299-302 - Anshul Sehgal, Ashish Jagmohan, Narendra Ahuja:
Wireless video conferencing using multiple description coding. 303-306 - Leonid B. Goldgeisser, Ernst Christen, Milan Vlach, Joachim Langenwalter:
Open ended dynamic ramping simulation of multi-discipline systems. 307-310 - Paolo Crippa, Massimo Conti, Claudio Turchetti:
A statistical methodology for the design of high-performance current steering DAC's. 311-314 - Gunther Reissig:
On methods for ordering sparse matrices in circuit simulation. 315-318 - Naveen Chandra, Gordon W. Roberts:
Top-down analog design methodology using Matlab and Simulink. 319-322 - Ahmed Fakhfakh, Noëlle Milet-Lewis, Yann Deval, Hervé Levi:
Study and behavioural simulation of phase noise and jitter in oscillators. 323-326 - Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
High-speed interconnect simulation using MIMO type of adaptive least square method. 327-330 - D. Strle:
Capacitor-area and power-consumption optimization of high-order Sigma-Delta modulators. 331-334 - Zongmou Yin:
Symbolic network analysis with the valid trees and the valid tree-pairs. 335-338 - Kiichiro Tsuji, A. Ohta:
An extended Petri net III and its applications. 339-342 - Massimo De Santo, Nicola Femia, Mario Molinara, Giovanni Spagnuolo:
Multi agent systems for circuit tolerance and sensitivity analysis. 343-346 - Yi-He Jiang, Jianbang Lai, Ting-Chi Wang:
Module placement with pre-placed modules using the B*-tree representation. 347-350 - Ingmar Neumann, Wolfgang Kunz:
Tight coupling of timing-driven placement and retiming. 351-354 - Habib Youssef, Sadiq M. Sait, Hussain Ali:
Adaptive bias simulated evolution algorithm for placement. 355-358 - Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz:
Cycle time optimization by timing driven placement with simultaneous netlist transformations. 359-362 - Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne:
Output transition time modeling of CMOS structures. 363-366 - Nitin Chandrachoodan, Shuvra S. Bhattacharyya, K. J. Ray Liu:
The hierarchical timing pair model. 367-370 - Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang:
Coupling-aware minimum delay optimization for domino logic circuits. 371-374 - Nadine Azémard, M. Aline, Daniel Auvergne:
Delay bound determination for timing closure satisfaction. 375-378 - Masanori Hashimoto, Hidetoshi Onodeva:
Increase in delay uncertainty by performance optimization. 379-382 - Dian Zhou, Wei Li, Wei Cai, Nailong Guo:
An efficient balanced truncation realization algorithm for interconnect model order reduction. 383-386 - Wei Li, Dian Zhou, Haksu Kim, Xuan Zeng:
Automatic clock tree design with IPs in the system. 387-390 - X. Zeng, D. Zhou:
Design of GHz VLSI clock distribution circuit. 391-394 - Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy:
Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. 395-398 - Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays. 399-402 - Dongho Kim, Tony Ambler:
Robust transition density estimation by considering input/output transition behavior. 403-406 - Jiwei Chen, Bingxue Shi:
Pulsed activation: Saving power for mixed-signal circuits. 407-410 - Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi:
Energy efficient signaling in DSM CMOS technology. 411-414 - Wen-Tsong Shiue:
Energy efficient memory assignment. 415-418 - Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
On the synthesis of cascaded continuous-time Sigma-Delta modulators. 419-422 - Yikui Dong, Ajoy Opal:
An overview on computer-aided analysis techniques for sigma-delta modulators. 423-426 - Hajime Shibata, Nobuo Fujii:
Analog circuit synthesis by superimposing of sub-circuits. 427-430 - Alex Doboli, Ranga Vemuri:
Hierarchical performance optimization for synthesis of linear analog systems. 431-434 - Nuno F. Paulino, João Goes, Adolfo Steiger-Garção:
Design methodology for optimization of analog building blocks using genetic algorithms. 435-438 - K. R. Whight:
A novel time domain method for computing phase noise in resonant oscillators. 439-442 - Yao-Lin Jiang, Richard M. M. Chen, Omar Wing:
A waveform relaxation approach to determining periodic responses of linear differential-algebraic equations. 443-446 - Akio Ushida, Yoshihiro Yamagami, Ikkei Kinouchi, Yoshifumi Nishio, Yasuaki Inoue:
An efficient algorithm for finding multiple DC solutions based on Spice oriented Newton homotopy method. 447-450 - Mark Zwolinski, R. W. Allen:
Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits. 451-454 - Kalle Folkesson, Christer Svensson, Jan-Erik Eklund:
Modeling of dynamic errors in algorithmic A/D converters. 455-458 - Zhen Mu:
Simulation and modeling of power and ground planes in high speed printed circuit boards. 459-462 - Kevin T. Tang, Eby G. Friedman:
Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. 463-466 - Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen:
A pattern compaction technique for power estimation based on power sensitivity information. 467-470 - Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen:
Grouped input power sensitive transition an input sequence compaction technique for power estimation. 471-474 - Nikolaos Nastos, Yannis Papananos:
A CAD tool for benchmarking MOSFET models. 475-478 - Karim S. Karim, Peyman Servati, N. Mohan, Arokia Nathan, John A. Rowlands:
VHDL-AMS modeling and simulation of a passive pixel sensor in a-Si: H technology for medical imaging. 479-482 - Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Gate-level simulation of CMOS circuits using the IDDM model. 483-486 - William H. Kao, Chi-Yuan Lo, Raminderpal Singh, Mark Basel:
Parasitic extraction: current state of the art and future trends. 487-490 - Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee:
A novel subcircuit extraction algorithm by recursive identification scheme. 491-494 - Q. Li, Sung-Mo Kang:
Trapezoid-to-simple polygon recomposition for resistance extraction. 495-498 - Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang:
ESD design rule checker. 499-502 - Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang:
Full chip ESD design rule checking. 503-506 - Daniel Eckerbert, Per Larsson-Edefors:
Cycle-true leakage current modeling for CMOS gates. 507-510 - Adrian Maxim, M. Gheorghe:
A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation. 511-514 - Medhat Karam, Wael Fikry, Hisham Haddara, Hani F. Ragai:
Implementation of hot-carrier reliability simulation in Eldo. 515-518 - Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh:
Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. 519-522 - Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai:
Synthesis of partition-codec architecture for low power and small area circuit design. 523-526 - Javier Sosa, Juan A. Montiel-Nelson, Saeid Nooshabadi:
Efficient computation of the area/power consumption versus delay tradeoff curve for circuit critical path optimization. 527-530 - Imed Ben Dhaou, N. Money, Hannu Tenhunen:
Fast low-power characterization of arithmetic units in DSM CMOS. 531-534 - Yi-Jong Yeh, Sy-Yen Kuo:
An optimization-based low-power voltage scaling technique using multiple supply voltages. 535-538
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