"Delay insensitivity verification of bit-level pipelined systolic arrays in ..."

Ayse Neslin Ismailoglu, Murat Askar (2008)

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DOI: 10.1109/ICECS.2008.4675040

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Ayse Neslin Ismailoglu, Murat Askar:
Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic. ICECS 2008: 1063-1066

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