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ORCIDYichao Zhang 0003
Person information
- affiliation: ETH Zurich, Integrated Systems Laboratory (IIS), Zurich, Switzerland
Other persons with the same name
- Yichao Zhang (aka: Yi-chao Zhang, Yi-Chao Zhang) — disambiguation page
- Yichao Zhang 0001
![[0000-0002-9931-4733]](https://devdomain4test.ir/img/orcid-mark.12x12.png "0000-0002-9931-4733")
— Tongji University, Department of Computer Sciences, DMB Lab, Shanghai, China - Yichao Zhang 0002 — University of Texas at Dallas, Richardson, TX, USA
- Yichao Zhang 0004 — DeepSeek-AI, Beijing, China
- Yichao Zhang 0005 — Chinese Academy of Sciences, Key Laboratory of Spectral Imaging Technology, Xi'an, China (and 1 more)
- Yichao Zhang 0006 — Aalborg University, AUU Energy, Aalborg, Denmark
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2020 – today
- 2026
[c13]Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
A 8.4 TFLOPS@16b/4.3W General-Purpose Programmable Accelerated Cluster for AI-Native RAN. CF 2026: 197-200- [i17]Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link. CoRR abs/2603.01629 (2026) - [i16]Marco Bertuletti, Yichao Zhang, Diyou Shen, Alessandro Vanelli-Coralli, Frank K. Gürkaynak, Luca Benini:
TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks. CoRR abs/2604.02291 (2026) - [i15]Yinrong Li, Zexin Fu, Yichao Zhang, Germain Haugou, Chi Zhang, Marco Bertuletti, Bowen Wang, Luca Benini:
Accelerating Precise End-to-End Simulation: Latency-Sensitive Many-core System Modeling. CoRR abs/2605.07750 (2026) - 2025
- [j3]Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. IEEE J. Solid State Circuits 60(4): 1324-1338 (2025) - [j2]Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link. IEEE Trans. Computers 74(11): 3667-3681 (2025) - [j1]Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks. IEEE Trans. Very Large Scale Integr. Syst. 33(8): 2225-2238 (2025) - [c12]Bowen Wang, Marco Bertuletti, Yichao Zhang, Victor J. B. Jung, Luca Benini:
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-Core RV Clusters for Attention-Based Model Deployment. ASAP 2025: 9-16 - [c11]Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini:
Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks. DAC 2025: 1-7 - [c10]Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini:
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs. DATE 2025: 1-7 - [c9]Mahdi Abdollahpour, Marco Bertuletti, Yichao Zhang, Yawei Li, Luca Benini, Alessandro Vanelli-Coralli:
A Compute&Memory Efficient Model-Driven Neural 5G Receiver for Edge AI-assisted RAN. GLOBECOM 2025: 5248-5253 - [c8]Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini:
TeraNOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters. ICCD 2025: 610-617 - [c7]Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini:
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication. IWASI 2025: 1-6 - [i14]Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. CoRR abs/2501.07330 (2025) - [i13]Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini:
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs. CoRR abs/2501.14370 (2025) - [i12]Sergio Mazzola, Yichao Zhang, Marco Bertuletti, Diyou Shen, Luca Benini:
MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster. CoRR abs/2504.03675 (2025) - [i11]Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini:
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication. CoRR abs/2507.05012 (2025) - [i10]Bowen Wang, Marco Bertuletti, Yichao Zhang, Victor J. B. Jung, Luca Benini:
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-core RV Clusters for Attention-Based Model Deployment. CoRR abs/2508.01180 (2025) - [i9]Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini:
TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters. CoRR abs/2508.02446 (2025) - [i8]Yichao Zhang, Marco Bertuletti, Sergio Mazzola, Samuel Riedel, Luca Benini:
A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN. CoRR abs/2509.08608 (2025) - 2024
- [c6]Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini:
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. DATE 2024: 1-6 - [c5]Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. ACM Great Lakes Symposium on VLSI 2024: 86-91 - [c4]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [i7]Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini:
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. CoRR abs/2401.04012 (2024) - [i6]Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini:
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. CoRR abs/2405.04988 (2024) - [i5]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR abs/2406.15068 (2024) - [i4]Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini:
A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR. CoRR abs/2408.08882 (2024) - 2023
- [c3]Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor. DATE 2023: 1-6 - [c2]Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. SAMOS 2023: 241-254 - [i3]Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. CoRR abs/2307.10248 (2023) - 2022
- [c1]Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini:
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI 2022: 44-49 - [i2]Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini:
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR abs/2209.00889 (2022) - [i1]Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini:
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor. CoRR abs/2210.09196 (2022)
Coauthor Index
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