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ORCIDIEEE Design & Test, Volume 30
Volume 30, Number 1, February 2013
- John F. Croix, Sunil P. Khatri, Kanupriya Gulati:
Using GPUs to Accelerate CAD Algorithms. 8-16 - Steven Hirsch, Ulrich Finkler:
To Thread or Not to Thread. 17-25 - Wei Wu, Fang Gong, Rahul Krishnan, Lei He, Hao Yu
:
Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms. 26-35 - Scott W. Wedge, Robert Daniels, Harald von Sosen:
Multicore Algorithms for Transient-Noise Simulation. 36-44 - Weiwei Chen, Xu Han, Che-Wei Chang, Rainer Dömer:
Advances in Parallel Discrete Event Simulation for Electronic System-Level Design. 45-54 - Patrick H. Madden:
Dispelling the Myths of Parallel Computing. 58-64 - Leon Stok:
Developing Parallel EDA Tools [The Last Byte]. 65-66 - Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Deploying Scan Chains for Data Storage in Test Compression Environment. 68-76
Volume 30, Number 2, April 2013
- Adam Waksman, Simha Sethumadhavan, Julianna Eum:
Practical, Lightweight Secure Inclusion of Third-Party Intellectual Property. 8-16 - Jim Aarestad, Philip Ortiz, Dhruva Acharyya, Jim Plusquellic:
HELP: A Hardware-Embedded Delay PUF. 17-25 - Kan Xiao, Xuehui Zhang, Mohammad Tehranipoor:
A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay. 26-34 - Jeyavijayan Rajendran, Arun K. Kanuparthi, Mohamed Zahran, Sateesh Addepalli, Gaston Ormazabal, Ramesh Karri:
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. 35-44 - Rajat Subhra Chakraborty, Indrasish Saha, Ayan Palchaudhuri, Gowtham Kumar Naik:
Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. 45-54 - Jason Oberg, Timothy Sherwood, Ryan Kastner:
Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip. 55-62 - Teresa L. McLaurin:
Creating Structural Patterns for At-Speed Testing: A Case Study. 66-76 - Hsuan-Ming Huang, Charles H.-P. Wen:
Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection. 77-86 - Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro:
Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction. 87-95
Volume 30, Number 3, June 2013
- Swarup Bhunia, Miron Abramovici, Dakshi Agrawal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, Mohammad Tehranipoor:
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution. 6-17 - Shaji Krishnan, Hans G. Kerkhoff:
Exploiting Multiple Mahalanobis Distance Metrics to Screen Outliers From Analog Product Manufacturing Test Responses. 18-24 - Samah Mohamed Saeed, Ozgur Sinanoglu:
Expedited-compact architecture for average scan power reduction. 25-33 - Abdelhakim Latoui, Farid Djahli:
An Optical BILBO for Online Testing of Embedded Systems. 34-48 - Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid:
Automatic Calibration of Streaming Applications for Software Mapping Exploration. 49-58 - Susann Wolf, Andy Heinig, Uwe Knöchel:
XML-Based Hierarchical Description of 3D Systems and SIP. 59-69 - Lars Liebmann, J. Andres Torres:
A Designer's Guide to Subresolution Lithography: Enabling the Impossible to Get to the 14-nm Node [Tutorial]. 70-92
Volume 30, Number 4, August 2013
- Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton:
Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. 8-15 - Arie Margulis, David Akselrod, Eric Rentschler, Mike Ricchetti:
Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs. 16-25 - Shobhit Malik, Thomas Herrmann, Sriram Madhavan, Rao Desineni, Chris Schuermyer, Geir Eide:
Deriving Feature Fail Rate from Silicon Volume Diagnostics Data. 26-34 - Sehun Kook, Aritra Banerjee, Abhijit Chatterjee:
Dynamic Specification Testing and Diagnosis of High-Precision Sigma-Delta ADCs. 36-48 - Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi:
A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. 49-59 - Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte:
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. 60-70 - Vincenzo Rana, Alessandro Antonio Nacci, Ivan Beretta, Marco D. Santambrogio, David Atienza, Donatella Sciuto:
Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms. 71-80 - Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker:
SAT-Based Analysis of Sensitizable Paths. 81-88
Volume 30, Number 5, October 2013
- Alfred L. Crouch, John C. Potter, Ajay Khoche, Jennifer Dworak:
FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System. 6-14 - Michele Portolan, Bradford G. Van Treuren, Suresh Goyal:
Executing IJTAG: Are Vectors Enough? 15-25 - Artur Jutman, Sergei Devadze, Konstantin Shibin:
Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. 26-35 - Martin Keim:
Thinking About Adopting IEEE P1687? 36-43 - Melanie Po-Leen Ooi, Hong Kuan Sok, Ye Chow Kuang, Huiyuan Cheng, Eric Kwang Joo Sim, Serge N. Demidenko, Chris W. K. Chan:
Identifying Systematic Failures on Semiconductor Wafers Using ADCAS. 44-53 - Zhenglin Liu, Qingchun Zhu, Dongfang Li, Xuecheng Zou:
Off-Chip Memory Encryption and Integrity Protection Based on AES-GCM in Embedded Systems. 54-62 - Sk Subidh Ali, Bodhisatwa Mazumdar, Debdeep Mukhopadhyay:
A Fault Analysis Perspective for Testing of Secured SoC Cores. 63-73 - Azadeh Davoodi, Min Li, Mohammad Tehranipoor:
A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection. 74-82
Volume 30, Number 6, December 2013
- Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De:
Adaptive and Resilient Circuits for Dynamic Variation Tolerance. 8-17 - Xingsheng Wang, Binjie Cheng, Jente B. Kuang, Andrew R. Brown, Campbell Millar, Asen Asenov:
Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology. 18-28 - Sumeet Kumar Gupta, Kaushik Roy:
Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs. 29-39 - Xiaoming Chen, Yu Wang, Huazhong Yang, Yuan Xie, Yu Cao:
Assessment of Circuit Optimization Techniques Under NBTI. 40-49 - Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung:
Variation and Reliability in FPGAs. 50-59 - Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Logic Circuits Under Timing Variations. 60-69 - Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura, Roberto Gómez:
Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. 70-79 - Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret:
Reduced-Code Linearity Testing of Pipeline ADCs. 80-88 - Selahattin Sayil, Sumanth R. Yeddula, Juyu Wang:
Single-Event Coupling Soft Errors in Nanoscale CMOS Circuits. 89-97 - Scott Davidson:
Planned Unobsolescence. 104
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