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ORCID2nd LATW 2001: Cancun, Mexico
- 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001. IEEE 2001
- Miron Abramovici:
Design for Testability Techniques: A Comparative Analysis. LATW 2001: 1 - Erik Jan Marinissen, Yervant Zorian:
Testing Embedded Core-Based System Chips. LATW 2001: 2 - Fabian Vargas, Alexandre M. Amory:
Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits. LATW 2001: 6-12 - Raoul Velazco, A. Bragagnini, Oscar Calvo:
Upset-like fault injection in VHDL descriptions: A Method and Preliminary Results. LATW 2001: 13-18 - Pablo A. Ferreyra, Carlos A. Marqués, Javier P. Gaspar, Ricardo T. Ferreyra:
A Software Tool for Simulating Single Event Upsets in a Digital Signal Processor. LATW 2001: 19-23 - Raoul Velazco, Sana Rezgui, Haissam Ziade:
Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied. LATW 2001: 24-29 - József Sziray:
A Test Calculation Principle for Logic and Timing Faults. LATW 2001: 32-37 - Anotnio Zenteno, Víctor H. Champac, Joan Figueras:
Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. LATW 2001: 38-44 - Paul Bizgambiglia, Dominique Federici, Jean François Santucci:
Fault Modeling and Simulation at Behavioral Level. LATW 2001: 45-50 - Luciano Hayato Ukuma, Eliane Martins:
Development of Self-Testing Software Components. LATW 2001: 52-55 - Sérgio Luis Cechin, Ingrid Jansch-Pôrto:
A New Efficient Coordinated Checkpointing. LATW 2001: 56-61 - Lívia Maria Rodrigues Sampaio Campos, Francisco Vilar Brasileiro:
Deploying Fault-Tolerant Processing Services for Asynchronous Distributed Systems. LATW 2001: 62-73 - Arturo Sarmiento-Reyes, Luis Hernadez Martinez:
Topological Considerations for the Diagnosability Conditions of Analogue CircuitsUsing a Pair of Conjugate Trees. LATW 2001: 76-79 - José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski:
Filter Sensitivity Analysis Using the TRAM. LATW 2001: 80-83 - José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski, Antonio Carneiro de Mesquita Filho:
Designing Testable Networks for Transfer Function Realization. LATW 2001: 84-87 - Vacius Jusas, Kestutis Paulikas, Rimantas Seinauskas:
Procedures for Selection of Validation Vectors on the Algorithm Level. LATW 2001: 90-95 - Ivor Ting, Andreas G. Veneris, Magdy S. Abadir:
ATPG Driven Logic Synthesis for Delay and Power Minimization. LATW 2001: 96-99 - Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick:
Sequential ATPG Using Combinational Algorithms. LATW 2001: 100-106 - Mani Soma:
Mixed-signal RF Design-for-Test: Is It R (Real) or F (Fake)? LATW 2001: 107 - Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. LATW 2001: 112-117 - Yukiya Miura:
Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits. LATW 2001: 118-125 - L. Cassol, Luigi Carro, Marcelo Lubaszewski:
The Sigma-Delta-Bist Method Applied to Linear Analog Circuits. LATW 2001: 126-130 - Gladys Omayra Ducoudray Acevedo, Jaime Ramírez-Angulo:
Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard. LATW 2001: 131-134 - Carlos Renato Lisboa Francês, Nandamudi Lankalapalli Vijaykumar, Regina Helena Carlucci Santana, Marcos José Santana, Solon Venâncio de Carvalho, Vakulathil Abdurahiman:
The Use of Analytical and Simulation Solutions with Statecharts for performance evaluation: A case study of a File Server model. LATW 2001: 136-141 - Luiz Angelo Barchet-Estefanel, Ingrind Jansch-Porto:
On the Evaluation of Heartbeat-like Detectors. LATW 2001: 142-147 - Adriano Brum Fontoura, Ingrid Jansch-Pôrto, Sérgio Luis Cechin:
Evaluating Approaches of Information Capturing from Applications Information. LATW 2001: 148-153 - Ilia Polian, Bernd Becker:
Multiple Scan Chain Design for Two-Pattern Testing. LATW 2001: 156-161 - Raimund Ubar:
Design Error Diagnosis in Scan-Path Designs. LATW 2001: 162-168 - Ismet Bayraktaroglu, Alex Orailoglu:
Improved Methods for Fault Diagnosis in Scan-Based BIST. LATW 2001: 169-172 - Jorge Marcos, Jacobo Álvarez, Enrique Mandado, Andres Nogueiras:
Failure Safe PLD Based Control System. LATW 2001: 174-179 - Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira:
Dynamically Rotate And Free for Test: The Path for FPGA Concurrent Test. LATW 2001: 180-185 - Miguel Angel Allende, Román Mozuelos, Mar Martínez, Salvador Bracho:
On Line IC Test Course With Distance Access to Test Equipment. LATW 2001 - Andreas Lechner, Martin John Burbidge, Andrew Richardson, B. Hermes:
3DB Challange for DfT, DfM, DOT & BIST Integration into Analogue and Mixed Signal ICs. LATW 2001: 194-199 - Bernard Courtois, Salvador Mir, Benoît Charlot, Marcelo Lubaszewski:
An Analog-based Approach for MEMS Testing. LATW 2001: 200-203 - Dave Bonnett:
IEEE 1149.1- The Internet of Test. LATW 2001: 204-208 - Joan Figueras:
Test Challenges in a Nanometric World. LATW 2001: 209 - Érika F. Cota, Luigi Carro, Marcelo Lubaszewski:
A Test Method for a Broad Class of DSP Circuits. LATW 2001: 214-219 - Janusz Sosnowski, Rafal Jurkiewicz:
Using On-Chip Monitors in Testing CPU Microarchitecture. LATW 2001: 220-225 - Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.:
Orienting Redundancy and HW/SW Codesign Techniques Towards Speech Recognition Systems. LATW 2001: 226-233 - José Luís Güntzel, Ana Cristina Medina Pinto, Ricardo Reis:
A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. LATW 2001: 234-239 - Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW 2001: 242-247 - Michael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian, Ben Chu, Tony Singh, Harvey Berman:
Designing and Implementing Efficient BISR Techniques for Embedded RAMs. LATW 2001: 248-252 - Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW 2001: 266-272 - Víctor H. Champac, Victor Avendaño, Gordana Jovanovic-Dolecek:
Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential Amplifier. LATW 2001: 273-276 - Luis C. R. Gonçalves, Paulo R. Rodegheri, Ricardo Augusto Manfredini, Taisy Silva Weber:
Testing Fault Tolerance Mechanisms in DBMS Through Fault Injection. LATW 2001: 278-284 - Luiz Carlos Pessoa Albini, Elias P. Duarte Jr.:
Generalized Distributed Comparison-Based System-Level Diagnosis. LATW 2001: 285-290
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