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ORCIDETS 2026: Chania, Greece
- IEEE European Test Symposium, ETS 2026, Chania, Greece, May 25-29, 2026. IEEE 2026, ISBN 979-8-3195-1763-0
- Vishal Thomas, Ussama Zahid, Giulio Gambardella, Sumeet Sapkal, Haralampos-G. Stratigopoulos, Brian Clerkin:
Towards Resilient Transformer-Encoders: Fault Injection and Hardware Agnostic Error Mitigation. 1-4 - Qiang Guo, Zixin Shen, Hongliang Lü, Liangliang Yu, Chunlin Ren, Junlin Huang:
Discovering Unknown Wafermap Patterns Using Cluster-Graph-Based Analytics. 1-4 - Emmanouil Anastasios Serlis, Emmanouil Arapidis, Theofilos Spyrou, Anteneh Gebregiorgis, Mottaqiallah Taouil, Said Hamdioui, Moritz Fieback:
Structural Testing Methodology for Deep Neural Networks based on RRAM. 1-4 - Phil Nigh:
How Testing must change in the age of AI processors, Silent Data Corruption Failures and 100s of Chiplets. 1 - Hakan Cetin, Alexandre Leon, Manuel J. Barragán, Philippe Ferrari:
Exploration of Machine Learning-Based Test Methodologies in High-Volume Manufacturing RF Testing. 1-6 - Ashwin Santhosh, Artur Jutman, Endri Kaja, Wolfgang Ecker, Maksim Jenihhin:
NURSE: A Distributed Architecture for Runtime Fault Management in Processor Designs. 1-4 - Michalis Kontos, Georgios Konstantinidis, Theocharis Theocharides, Maria K. Michael:
ARMOR: Architectural Reliability via Multi-Objective Optimization for Early-Exit Neural Networks. 1-4 - Letícia Maria Bolzani Pöhls:
Exploring Hybrid Brain-Inspired Architectures and Technology Heterogeneity for High Performance AI Applications: Challenges & Solutions. 1-6 - Paolo Bernardi, Lorenzo Cardone, Stefano Quer:
Fast Circuit Analysis via Neighborhood-Guided Maximum Common Subgraph. 1-6 - Kazuyuki Iwaguro:
Leading-Edge Test Technology and Strategies for Automotive Products. 1 - Simone Anedda, Paolo Bernardi, Matteo Coppetta, Giorgio Insinga, Tommaso Montedoro, Annachiara Ruospo, Rudolf Ullmann, Felix Tengler:
Off-Chip Super-Resolution AI Model to Support Embedded Memory Diagnosis. 1-6 - David C. Keezer, Cao Wang, Shengbo Liu, Xiaochun Li, Yindong Xiao:
Extending FPGA-based NRZ Test Signals Beyond 100 Gbps. 1-6 - Ruize Wang, Linus Backlund, Elena Dubrova:
A Chosen-Ciphertext Side-Channel Attack on Protected ML-KEM Using Pairwise Bit-Flipping. 1-6 - Fouwad Jamil Mir, Asmae El Arrassi, Said Hamdioui, Mottaqiallah Taouil:
A CIM-based Gaussian Random Number Generator for Edge Devices as Security Primitive. 1-4 - Dillibabu Shanmugam, Zhenyuan Liu, Patrick Schaumont:
Hierarchical EMFI Analysis on a RISC-V SoC. 1-4 - Simon Schupp, Tara Gheshlaghi, Priyanjana Pal, Mehdi B. Tahoori:
FAT-SNN: Fault-Aware Training of Flexible Analog Spiking Neural Networks Using Robust Surrogates. 1-6 - Marc Margalef-Rovira, Loïc Vincent, Emmanuel Pistono, Sylvain Bourdel, Manuel J. Barragán, Philippe Ferrari:
Oscillation-Based Test for mm-Wave Reflection-Type Phase Shifters. 1-6 - Antonio Emmanuele, Mario Barbareschi, Alberto Bosio:
Test Sample Ranking for Fault Detection in Decision Tree-based Inference Model. 1-6 - Luc Romain, Katarzyna Wojnowska, Roger Mah, Albert Au, Wei Zou, Martin Keim:
An Enhanced, Self-Adapting Asynchronous Interface for High-Frequency IJTAG Instruments In Clock Mesh Environments. 1-6 - Konstantinos Varakliotis, Nikolaos Zazatis, Marko S. Andjelkovic, Nikolaos Chatzivangelis, Fabian Vargas, Milos Krstic, Christos P. Sotiriou:
Machine Learning Approach for Cross-Technology Prediction of the Generated Single Event Transient. 1-4 - Daniel Thirion, George-Cristian Sercaianu, Valentin Egloff, Jean-Marc Daveau, Vincent Beroulle, David Hély, Philippe Roche:
Fault Model-Driven Formal Verification of Cryptographic Hardware Against Fault Attacks. 1-6 - Sandeep Kumar Goel:
Shaping the Future of Multi-Die Stacking: Overcoming Challenges through Collaboration and Standards. 1 - Manan Kumar Singh, Gaurav Kumar, Kashvi Bansal, Yamuna Prasad, Satyadev Ahlawat:
On Evaluating the Security of TRNG-driven SRAM Scrambling Architecture. 1-6 - Pei-Yun Lin, Jin-Fu Li:
Exploration of Reference Trimming Schemes for STT-MRAMs. 1-4 - Wim Nijsink, Bruno Endres Forlin, Amirreza Yousefzadeh, Marco Ottavi:
Shooting Neutrons at Neurons: Radiation Testing of a Spiking Neural Network on Flash-Based FPGAs. 1-4 - Nikolaos Chatzivangelis, Marios Karagiannis, Christos Georgakidis, Nikolaos Sketopoulos, Marko S. Andjelkovic, Luigi Dilillo, Christos P. Sotiriou:
STA-Based Single Event Transient Propagation in Advanced Technology Nodes. 1-4 - Evangelos Paparsenos, Yiorgos Tsiatouhas:
Radiation Hardened and Self-Recoverable Latch Design for Quad-Node Upset Mitigation. 1-4 - Fouwad Jamil Mir, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil:
SWEET-DREAM: Side-Channel Weakness Evaluation and Enhanced Mitigation for DREAM-CIM. 1-6 - Soyed Tuhin Ahmed, Krishnendu Chakrabarty, Jin-Fu Li, Mottaqiallah Taouil, Fouwad Jamil Mir, Said Hamdioui, Mehdi B. Tahoori, Martin Keim, Jongsin Yun:
Reliability, Test, and Security of Compute-In-Memories. 1-9 - Elijah Seth Cishugi
, Kuan-Hsun Chen, Marco Ottavi:
Efficient Hash-to-Index via Rejection Sampling for Online Fault Detection with Bloom/Cuckoo Filters. 1-6 - Sabrina Ait Belkacem, Lila Ammoura, Maria Ramirez-Corrales, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
Exploiting Near-Memory Computing Resources for Native, Adaptive, and Low-Overhead MBIST. 1-4 - Hsiao-Ping Ni, Eduardo Ortega, Krishnendu Chakrabarty:
EXACT: Edge-eXplainable Autonomous Causal Telemetry for Silicon Lifecycle Management. 1-6 - Zhicheng Shao, Xiaole Cui, Xiaoxin Cui:
An Elmore Delay Model Based Test Method for Post-Bond TSVs. 1-6 - Leonidas Kosmidis, Sergi Alcaide, Matina Maria Trompouki, Antonio Escobar-Molero, Adam Anglart, Daniel Van Geest, Martin Zuber, Jean-Paul Truong, Andrej Grebenc, Detlef Houdeau:
Introduction to Post Quantum Cryptography for Resource Constrained Systems. 1-7 - Madiha A. Sheikh, Marco Ottavi:
A Single-Cycle, Area-Efficient Calibration Method for TDC-based Timing Monitors. 1-6 - Lawrence M. Schlitt, Priyank Kalla, Steve Blair:
Scalable Design-for-Calibration of Programmable Silicon Photonics. 1-6 - Lina Baolati, Wenjing Rao, Natasha Devroye:
Beyond Fingerprints: Systematic Design of APUFs for Batch Identification. 1-4 - Tim Strobel, Nima Shahpari, Sarah Rottacker, Roland Rösslhuber, Jens Anders:
Sample-efficient Performance Tuning of mixed-signal ASICs via Probabilistic Surrogates. 1-6 - Yonghao Wang, Jiaxin Zhou, Yang Yin, Hongqin Lyu, Zhiteng Chao, Wenchao Ding, Jing Ye, Tiancheng Wang, Huawei Li:
Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification. 1-6 - Anthony Coyette, Wim Dobbelaere, Doina Dima, Arlind Billa, Krzysztof Jurga, Vladimir Zivkovic, Stephen Sunter:
Testing of a 12 bit SARA And Cand Analog Scan. 1-6 - Joel Åhlund, Fanny Lundberg, Markus Törmänen, Erik Larsson:
Attacks Exploiting On-Chip Instruments and IJTAG Protection. 1-4 - Md Fahim Ul Islam, Krishnendu Chakrabarty:
SOLDER: State-Space Oriented Learning with Denoising-Enhanced Representations for PCB Defect Analysis. 1-4 - Alexandru Ciobotaru, Cosmina Corches, Dan Gota, Szilárd Enyedi, Ovidiu Stan, Liviu Miclea:
Robustness Assessment of Edge AI-Based Li-Ion Battery State-Of-Health Prediction. 1-6 - Giorgio Di Natale, Emanuele Valea:
Hardware Trojans Horses: Two Decades Later, What We Really Know. 1-10 - Anshuman Chandra, Moiz Khan, Barbara Dzialowska, Marta Stepniewska:
A Circular Repair Scheme for 3DIC Die-to-Die Interconnects. 1-6 - Yang Yang, Bin Yang, Yiwen Liao Data:
An interpretable data-driven framework for variable group selection in high-dimensional manufacturing test data. 1-6 - Marcello Barbirotta, Marco Angioli, Rocco Martino, Federico Frontera, Antonio Mastrandrea, Mauro Olivieri:
Impact and Characterization of Single Event Failures in Hyperdimensional Computing Hardware Accelerator. 1-4 - Marco D'Acunzo, Daniele Rossi, Jamal Mohamad Maamoun, Giorgia Cassetta:
Use of GitHub Copilot Agent Mode for Automated Development in R&D Data Engineering. 1-4 - Asmaa Kassimi, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil:
Bridging the Speed-Accuracy Gap: Layout-Aware Pre-Silicon Side-Channel Analysis. 1-4 - Lucas Rhetat, Jean-Philippe Noel, Bastien Giraud, Laurent Grenouillet, Cédric Marchand, Ian O'Connor:
A Ferroelectric nvSRAM PUF with Built-In Grey Bit Masking based on FeCAP-SRAM Interactions. 1-6 - Martha Schnieber, Rolf Drechsler:
Path Delay Fault Testable KFDD Circuits with Polynomial Test Pattern Generation. 1-4 - Sajjad Parvin, Carl Riehm, Nan Du, Ralf Brederlow, Frank Sill Torres, Rolf Drechsler:
Special Session: Hardware Security at the Circuit and Layout Levels. 1-8 - Panagiotis Chaidos, Alexis Maras, Georgios Alexandris, Dimitrios Soudris, Sotirios Xydis:
Soft-Error Sensitivity Analysis of Adder Tree architectures for Compute-In-Memory Accelerators. 1-4 - Vladimir A. Zivkovic, Stephan Eggersglüß, Andreas Glowatz, Daniel Tille:
TDDB Stress Test Coverage Quantification using Cell-aware Transistor State Stress Model. 1-6 - Larisa Goffman-Vinopal:
Actuarial Voltage Scaling (AVS+): A Statistical Reliability Framework for Reducing Guardbands in Systolic Arrays. 1-4 - Ashish Reddy Bommana, Anshuman Chandra, Moiz Khan:
Encoded Repair Configuration Chains for Die-to-Die Interconnect Test and Repair Language. 1-4 - Shyue-Kung Lu, Qian-Rui Dong:
Re-sequencing ECC and Built-In Self-Repair with In-Page Fault Scrambling for Enhancing Yield and Reliability of Flash Memory. 1-4 - Paula Carolina Lozano Duarte, Sule Ozev, Mehdi B. Tahoori:
Distributed Delay-Based BIST for Mixed-Signal Circuits in Flexible Electronics. 1-4 - Francesco Angione, Paolo Bernardi, Nicola Di Gruttola Giardino, Gabriele Filipponi, Giusy Iaria, Giacomo Perlo, Irith Pomeranz, Antonio Porsia, Annachiara Ruospo, Ernesto Sánchez, Vittorio Turco:
Advances in Testing and Reliability Benchmarks. 1-10 - Haneen G. Hezayyin, Mahta Mayahinia, Mehdi B. Tahoori, Sule Ozev:
TDsReCAM: Time-Domain sensing for reliable ReRAM-based Content Addressable Memory. 1-6 - Shyue-Kung Lu, Chin-Jung Lee:
Design-for-Testability and Built-In Self-Test Techniques for SRAM-Based Compute-In-Memory Systems. 1-4 - Leandro Lanzieri, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt:
Auto-Generating Ageing Self-Tests with Hardware in the Loop for Commercial Microcontrollers. 1-4 - Ankush, Ashiqur Rasul, Anurup Saha, Abhijit Chatterjee:
CODA: Confidence-Driven Adaptive Testing of Analog/Mixed-Signal Circuits Using Gaussian Mixture Models. 1-6 - Bartlomiej Praselski, Stephen Sunter:
Using Analog IJTAG to Measure ISO 26262 Metrics. 1-6 - Mottaqiallah Taouil, R. D. Shawn Blanton, Phil Nigh, Adit D. Singh, Said Hamdioui:
Gremlins in the Silicon: Why Faulty Chips are Escaping the Fab and Crashing in the Field. 1-10 - Elia Lazzeri, Gianluca Furano, Luca Cassano:
A real opportunity or still a promise? The current status of the RISC-V ecosystem. 1-9 - Wei Zou, Artur Pogiel, Martin Keim, Albert Au, Jongsin Yun, Luc Romain:
Memory ECC Logic Testing using MBIST. 1-4 - Sara Mannaa, Grégory Loubet, Salvatore Pappalardo, Cédric Marchand, Damien Deleruyelle, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Yifan Wang, François Marc, Chhandak Mukherjee, Marina Deng, Cristell Maneux, Ian O'Connor:
A Holistic Framework to Assess Reliability Issues in Emerging Technologies due to Ageing, Voltage and Temperature Variation. 1-6
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last updated on 2026-07-23 22:10 CEST by the dblp team
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