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ORCID"I-COR: Instruction-Level Fault Tolerance for Register File in 3-Stage ..."
- Zewen Cao
, Ying Yang, Qi Wang:
I-COR: Instruction-Level Fault Tolerance for Register File in 3-Stage Pipeline RISC-V Processors. ACM Trans. Embed. Comput. Syst. 25(2): 30:1-30:25 (2026)
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