"A hybrid design-time/run-time scheduling flow to minimise the ..."

Javier Resano et al. (2004)

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DOI: 10.1016/J.MICPRO.2004.03.015

access: closed

type: Journal Article

metadata version: 2020-05-18

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Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor:
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. Microprocess. Microsystems 28(5-6): 291-301 (2004)

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