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ORCID"Full-chip subthreshold leakage power prediction and reduction techniques ..."
- Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan:
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. IEEE J. Solid State Circuits 39(3): 501-510 (2004)
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