"A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs ..."

Yen-Po Lin et al. (2026)

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DOI: 10.1109/JSSC.2025.3562885

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type: Journal Article

metadata version: 2026-02-17

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Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh:
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS. IEEE J. Solid State Circuits 61(2): 423-433 (2026)

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