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"An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Tetsutaro Hashimoto et al. (2018)

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DOI: 10.1109/JSSC.2017.2777101

access: closed

type: Journal Article

metadata version: 2020-08-30

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Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita:
An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. IEEE J. Solid State Circuits 53(4): 1028-1037 (2018)

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