"A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm ..."

Mohamed M. Elsayed et al. (2011)

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DOI: 10.1109/JSSC.2011.2156990

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type: Journal Article

metadata version: 2020-08-30

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Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio:
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator. IEEE J. Solid State Circuits 46(9): 2084-2098 (2011)

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