"χ RVFormal: Formal verification of RISC-V processor Chisel designs."

Shidong Shen et al. (2026)

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DOI: 10.1016/J.SYSARC.2026.103761

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type: Journal Article

metadata version: 2026-04-26

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Shidong Shen, Shijie Chen, Yicheng Liu, Lijun Zhang, Fu Song, Zhilin Wu:
χ RVFormal: Formal verification of RISC-V processor Chisel designs. J. Syst. Archit. 175: 103761 (2026)

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