"A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology."

Ching-Che Chung, Duo Sheng, Chia-Lin Chang (2011)

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DOI: 10.1587/ELEX.8.518

access: open

type: Journal Article

metadata version: 2025-10-14

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Ching-Che Chung, Duo Sheng, Chia-Lin Chang:
A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. IEICE Electron. Express 8(7): 518-524 (2011)

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