"Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some ..."

Kuntal Roy (2007)

> Home

Details and statistics

DOI: 10.2498/CIT.1000731

access: closed

type: Journal Article

metadata version: 2022-08-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/cit/Roy07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/cit/Roy07
Kuntal Roy:
Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations. J. Comput. Inf. Technol. 15(1): 85-92 (2007)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.