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ORCID"A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved ..."
- Kyoung-Ub Cho
, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun Seong Kim, Yun Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh:
A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process. IEEE Access 12: 142677-142694 (2024)
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