default search action

combined dblp search
author search
venue search
publication search

ask others

"A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Rishabh Mittal et al. (2023)

> Home

Details and statistics

DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185279

access: closed

type: Conference or Workshop Paper

metadata version: 2026-02-01

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/MittalSPKSMCL23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/MittalSPKSMCL23
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits 2023: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.

last updated on 2026-02-01 13:33 CET by the dblp team

all metadata released as open data under CC0 1.0 license

see also: Terms of Use | Privacy Policy | Imprint

dblp was originally created in 1993 at:

since 2018, dblp has been operated, funded, and maintained by:

Schloss Dagstuhl - Leibniz Center for Informatics is a member of the Leibniz Association and is funded by the federal government of Germany and the states of Germany, especially Saarland and Rhineland‑Palatinate.