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"A Novel Low Power Ternary Multiplier Design using CNFETs."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Harita Sirugudi, Sharvani Gadgil, Chetan Kumar Vudadha (2020)

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DOI: 10.1109/VLSID49098.2020.00022

access: closed

type: Conference or Workshop Paper

metadata version: 2026-04-19

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/SirugudiGV20
Harita Sirugudi, Sharvani Gadgil, Chetan Kumar Vudadha:
A Novel Low Power Ternary Multiplier Design using CNFETs. VLSID 2020: 25-30

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