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"A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Vinay Kumar et al. (2017)

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DOI: 10.1109/VLSID.2017.17

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/KumarPKS17
Vinay Kumar, Nikhil Puri, Sudhir Kumar, Sumit Srivastav:
A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET. VLSID 2017: 269-274

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last updated on 2023-03-24 00:03 CET by the dblp team

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