"A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry ..."

Chetan Deshpande et al. (2021)

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DOI: 10.23919/VLSICIRCUITS52068.2021.9492464

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-02

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Chetan Deshpande, Ritesh Garg, Gajanan Jedhe, Gaurang Narvekar, Sushil Kumar:
A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs. VLSI Circuits 2021: 1-2

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