"Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap."

Venkata Appa Rao Yempada, Srivatsava Jandhyala (2019)

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DOI: 10.1007/978-981-32-9767-8_59

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-21

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Venkata Appa Rao Yempada, Srivatsava Jandhyala:
Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap. VDAT 2019: 716-726

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