"An all digital delay lock loop architecture for high precision timing ..."

Mohammad Waris et al. (2015)

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DOI: 10.1109/ISVDAT.2015.7208138

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Mohammad Waris, Urvi Mehta, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury:
An all digital delay lock loop architecture for high precision timing generator. VDAT 2015: 1-6

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