"Optimized Test Pattern Generation for Digital Circuits using SAT-Based ..."

Sandra Sugathan, Adersh V. R (2024)

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DOI: 10.1109/VDAT63601.2024.10705671

access: closed

type: Conference or Workshop Paper

metadata version: 2024-11-20

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Sandra Sugathan, Adersh V. R:
Optimized Test Pattern Generation for Digital Circuits using SAT-Based ATPG and Scan Insertion Method. VDAT 2024: 1-6

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