"A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with ..."

Vishal Sharma et al. (2018)

> Home

Details and statistics

DOI: 10.1007/978-981-13-5950-7_46

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vdat/SharmaBDCJV18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vdat/SharmaBDCJV18
Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma:
A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. VDAT 2018: 551-564

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.