"Design and ASIC Implementation of Area Efficient UART Core in SCL 180nm ..."

Arjun J. M, Titto Anujan (2024)

> Home

Details and statistics

DOI: 10.1109/VDAT63601.2024.10705725

access: closed

type: Conference or Workshop Paper

metadata version: 2025-03-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vdat/MA24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vdat/MA24
Arjun J. M, Titto Anujan:
Design and ASIC Implementation of Area Efficient UART Core in SCL 180nm Technology. VDAT 2024: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.