"An RTL power optimization technique based on System Verilog assertions."

Khaled Khalifa, Khaled Salah (2016)

> Home

Details and statistics

DOI: 10.1109/UEMCON.2016.7777857

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/uemcom/KhalifaS16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/uemcom/KhalifaS16
Khaled Khalifa, Khaled Salah:
An RTL power optimization technique based on System Verilog assertions. UEMCON 2016: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.