"Force Rebalance with Multi-bit Sigma-Delta implemented with FPGA for ..."

George P. Rajesh et al. (2019)

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DOI: 10.1109/TENCON.2019.8929279

access: closed

type: Conference or Workshop Paper

metadata version: 2019-12-18

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George P. Rajesh, C. K. Deepthy, M. Mary Jermila, K. P. Raghunath, Vishnu N. Aparna:
Force Rebalance with Multi-bit Sigma-Delta implemented with FPGA for Precision Rate Sensor. TENCON 2019: 654-657

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