"FPGA implementation of layered low density parity check error correction ..."

Abdulsamet Caglan et al. (2017)

> Home

Details and statistics

DOI: 10.1109/SIU.2017.7960719

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/siu/CaglanBKCCC17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/siu/CaglanBKCCC17
Abdulsamet Caglan, Ersen Balcisoy, Emre Kirkaya, Gurbannazar Charyyev, Adem Çiçek, Enver Cavus:
FPGA implementation of layered low density parity check error correction codes. SIU 2017: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.