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"Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

A. Cortiula et al. (2025)

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DOI: 10.1109/PRIME66228.2025.11203302

access: closed

type: Conference or Workshop Paper

metadata version: 2026-06-21

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/prime/CortiulaSMMBDP25
A. Cortiula, D. Scubla, S. Murra, Davide Menin, Andrea Bandiziol, Francesco Driussi, Pierpaolo Palestri:
Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS. PRIME 2025: 1-4

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