"Parallel Test Pattern Generation Using Circuit Partitioning in a ..."

Consolación Gil et al. (1998)

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DOI: 10.1007/BFB0095334

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-08

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Consolación Gil, Julio Ortega, José Luis Bernier, Maria Dolores Gil Montoya:
Parallel Test Pattern Generation Using Circuit Partitioning in a Shared-Memory Multiprocessor. PARA 1998: 167-171

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