"A case study on applying bounded model checking to analog circuit ..."

Alexander Jesser et al. (2006)

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DOI: —

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type: Conference or Workshop Paper

metadata version: 2012-06-28

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  dblp key:
  - conf/mbmv/JesserWHK06
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  persistent URL:
  - https://dblp.org/rec/conf/mbmv/JesserWHK06
Alexander Jesser, Markus Wedler, Lars Hedrich, Wolfgang Kunz:
A case study on applying bounded model checking to analog circuit verification. MBMV 2006: 106-113

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