"Validating the performance of a 32nm CMOS high speed serial link receiver ..."

Sudeep Puligundla et al. (2010)

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DOI: 10.1109/TEST.2010.5699242

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran:
Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. ITC 2010: 405-409

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