"Rapid FPGA delay characterization using clock synthesis and sparse sampling."

Mehrdad Majzoobi et al. (2010)

> Home

Details and statistics

DOI: 10.1109/TEST.2010.5699248

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/itc/MajzoobiDEK10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc/MajzoobiDEK10
Mehrdad Majzoobi, Eva L. Dyer, Ahmed Elnably, Farinaz Koushanfar:
Rapid FPGA delay characterization using clock synthesis and sparse sampling. ITC 2010: 457-466

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.