"Low power test application with selective compaction in VLSI designs."

Dariusz Czysz, Janusz Rajski, Jerzy Tyszer (2012)

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DOI: 10.1109/TEST.2012.6401532

access: closed

type: Conference or Workshop Paper

metadata version: 2025-05-01

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Dariusz Czysz, Janusz Rajski, Jerzy Tyszer:
Low power test application with selective compaction in VLSI designs. ITC 2012: 1-10

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