"Minimization of Circuit Delay and Power through Gate Sizing and Threshold ..."

Shuzhe Zhou et al. (2011)

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DOI: 10.1109/ISVLSI.2011.29

access: closed

type: Conference or Workshop Paper

metadata version: 2026-01-15

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Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai:
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI 2011: 212-217

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