"500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC ..."

Menka Sukhwani et al. (2011)

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DOI: 10.1109/ISVLSI.2011.56

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

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Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda:
500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti". ISVLSI 2011: 72-77

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