"Scalable Resonant Power Clock Generation for Adiabatic Logic Design."

Ragh Kuttappa et al. (2021)

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DOI: 10.1109/ISVLSI51109.2021.00068

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-30

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Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin:
Scalable Resonant Power Clock Generation for Adiabatic Logic Design. ISVLSI 2021: 338-342

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