"A 0.0056mm2 all-digital MDLL using edge re-extraction, ..."

Shiheng Yang et al. (2018)

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DOI: 10.1109/ISSCC.2018.8310212

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-20

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Shiheng Yang, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A 0.0056mm² all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. ISSCC 2018: 118-120

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