"15.2 A 350mV Single-Rail SRAM Using a Custom-Logic-Bitcell in ..."

Manish Trivedi et al. (2026)

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DOI: 10.1109/ISSCC49663.2026.11409350

access: closed

type: Conference or Workshop Paper

metadata version: 2026-03-26

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Manish Trivedi, Sandipan Sinha, Ramesh Halli, Girishankar Gurumurthy, Jaswinder Singh, Chun-Yuan Cheng, Linchien Chen, Jeff Lin, Hugh Mair:
15.2 A 350mV Single-Rail SRAM Using a Custom-Logic-Bitcell in 2nm-CMOS-Nanosheet Technology for Mobile and Edge-AI Applications. ISSCC 2026: 256-258

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