"8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital ..."

Daniel Coombs et al. (2017)

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DOI: 10.1109/ISSCC.2017.7870306

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu:
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. ISSCC 2017: 152-153

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