"Chip Package Co-design and Physical Verification for Heterogeneous ..."

Rajsaktish Sankaranarayanan et al. (2021)

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DOI: 10.1109/ISQED51717.2021.9424318

access: closed

type: Conference or Workshop Paper

metadata version: 2021-05-17

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Rajsaktish Sankaranarayanan, Archanna Srinivasan, Arch Zaliznyak, Sreelekha Mittai:
Chip Package Co-design and Physical Verification for Heterogeneous Integration. ISQED 2021: 275-279

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