"Simultaneous buffer insertion and non-Hanan optimization for VLSI ..."

Jiang Hu, Sachin S. Sapatnekar (1999)

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DOI: 10.1145/299996.300041

access: closed

type: Conference or Workshop Paper

metadata version: 2025-11-20

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Jiang Hu, Sachin S. Sapatnekar:
Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138

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