"Analysis and design considerations of static CMOS logics under process, ..."

Wei-Bin Yang et al. (2015)

> Home

Details and statistics

DOI: 10.1109/ISPACS.2015.7432737

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ispacs/YangLWCCL15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ispacs/YangLWCCL15
Wei-Bin Yang, Yu-Yao Lin, Chi-Hsiung Wang, Kuo-Ning Chang, Cing-Huan Chen, Yu-Lung Lo:
Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process. ISPACS 2015: 57-61

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.