"A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection ..."

Yoshifumi Kawamura et al. (2015)

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DOI: 10.1109/ISPACS.2015.7432795

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda:
A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. ISPACS 2015: 351-356

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